NXP Semiconductors MKL25Z128VLK4 - Page 327

19.3.3 System ROM Memory Map
The System ROM Table registers are also mapped into a sparsely-populated 4 KB
address space.
For core configurations like that supported by Cortex-M0+, ARM recommends that a
debugger identifies and connects to the debug components using the CoreSight debug
infrastructure.
ARM recommends that a debugger follows the flow as shown in the following figure to
discover the components in the CoreSight debug infrastructure. In this case a debugger
reads the peripheral and component ID registers for each CoreSight component in the
CoreSight system.
Figure 19-56. CoreSight discovery process
ROM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F000_2000 Entry (ROM_ENTRY0) 32 R See section 19.33.1/328
F000_2004 Entry (ROM_ENTRY1) 32 R See section 19.33.1/328
F000_2008 Entry (ROM_ENTRY2) 32 R See section 19.33.1/328
F000_200C End of Table Marker Register (ROM_TABLEMARK) 32 R 0000_0000h 19.33.2/329
F000_2FCC System Access Register (ROM_SYSACCESS) 32 R 0000_0001h 19.33.3/329
F000_2FD0 Peripheral ID Register (ROM_PERIPHID4) 32 R See section 19.33.4/330
F000_2FD4 Peripheral ID Register (ROM_PERIPHID5) 32 R See section 19.33.4/330
F000_2FD8 Peripheral ID Register (ROM_PERIPHID6) 32 R See section 19.33.4/330
Table continues on the next page...
Chapter 19 Micro Trace Buffer (MTB)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 327