Table 3-27. KL25 flash memory size (continued)
Device Program flash (KB) Block 0 (P-Flash) address range
MKL25Z128VFM4 128 0x0000_0000 – 0x0001_FFFF
MKL25Z32VFT4 32 0x0000_0000 – 0x0000_7FFF
MKL25Z64VFT4 64 0x0000_0000 – 0x0000_FFFF
MKL25Z128VFT4 128 0x0000_0000 – 0x0001_FFFF
MKL25Z32VLH4 32 0x0000_0000 – 0x0000_7FFF
MKL25Z64VLH4 64 0x0000_0000 – 0x0000_FFFF
MKL25Z128VLH4 128 0x0000_0000 – 0x0001_FFFF
MKL25Z32VLK4 32 0x0000_0000 – 0x0000_7FFF
MKL25Z64VLK4 64 0x0000_0000 – 0x0000_FFFF
MKL25Z128VLK4 128 0x0000_0000 – 0x0001_FFFF
3.6.1.2 Flash Memory Map
The flash memory and the flash registers are located at different base addresses as shown
in the following figure. The base address for each is specified in System memory map.
Program flash
Flash configuration field
Program flash base address
Flash memory base address
Registers
Figure 3-17. Flash memory map
The on-chip Flash is implemented in a portion of the allocated Flash range to form a
contiguous block in the memory map beginning at address 0x0000_0000. See Flash
Memory Sizes for details of supported ranges.
Accesses to the flash memory ranges outside the amount of Flash on the device causes
the bus cycle to be terminated with an error followed by the appropriate response in the
requesting bus master. Read collision events in which flash memory is accessed while a
flash memory resource is being manipulated by a flash command also generates a bus
error response.
3.6.1.3 Flash Security
How flash security is implemented on this device is described in Chip Security.
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 73
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