Omron CQM1H - PROGRAM User Manual

28
Interrupt Functions Section 1-4
If the Counter Mode is not used, these SR bits can be used as work bits.
2. With the INT(89) instruction, refresh the Counter Mode set value and en-
able interrupts.
The input interrupt for which the set value is refreshed will be enabled in
Counter Mode. When the counter reaches the set value, an interrupt will
occur, the counter will be reset, and counting/interrupts will continue until the
counter is stopped.
Note 1. If the INT(89) instruction is used during counting, the present value (PV)
will return to the set value (SV). You must, therefore, use the differentiated
form of the instruction or an interrupt may never occur.
2. The set value will be set when the INT(89) instruction is executed. If inter-
rupts are already in operation, then the set value will not be changed just
by changing the content of SR 244 to SR 247, i.e., if the contents is
changed, the set value must be refreshed by executing the INT(89) instruc-
tion again.
Interrupts can be masked using the same process as for the Input Interrupt
Mode, but if the masks are cleared using the same process, the Counter
Mode will not be maintained and the Input Interrupt Mode will be used
instead. Interrupt signals received for masked interrupts can also be cleared
using the same process as for the Input Interrupt Mode.
Counter PV in Counter Mode
When input interrupts are used in Counter Mode, the counter PV will be
stored in the SR word corresponding to input interrupts 0 to 3. Values are
0000 to FFFE (0 to 65,534) and will equal the counter PV minus one.
Example: The present value for an interrupt whose set value is 000A will be
recorded as 0009 immediately after INT(89) is executed.
Note Even if input interrupts are not used in Counter Mode, these SR bits cannot be
used as work bits.
(@)INT(89)
003
000
D
If D bits 0 to 3, which correspond to input interrupts 0 to 3,
are set to "0," then the set value will be refreshed and inter-
rupts will be permitted.
0: Counter mode set value refreshed and mask cleared.
1: Nothing happens. (Set to 1 the bits for all interrupts
that are not being changed.)
Interrupt Word containing counter PV – 1
Input interrupt 0 SR 248
Input interrupt 1 SR 249
Input interrupt 2 SR 250
Input interrupt 3 SR 251

Omron CQM1H - PROGRAM Specifications

General

I/O Capacity	Up to 512 points
Power Supply	100 to 240 VAC, 50/60 Hz or 24 VDC (depending on model)
Instruction Set	Basic and advanced instructions
Operating Temperature	0 to 55°C
Program Capacity	7.2K to 15.2K steps
Communication Ports	RS-232C
Expansion Slots	Up to 3 expansion units
Type	Programmable Logic Controller (PLC)
CPU Type	RISC
Program Memory	7.2K to 15.2K steps
I/O Points	512 max
Expansion Capability	Up to 3 expansion units
Data Memory	RAM (battery backup)

Summary

PRECAUTIONS

1 Intended Audience

Specifies the target personnel for this manual, requiring knowledge of electrical systems and FA systems.

2 General Precautions

Outlines user responsibilities for operating the product according to specifications and consulting representatives for specific applications.

3 Safety Precautions

Details critical safety warnings related to I/O refreshing, touching internal components, disassembly, and power supply handling.

5 Application Precautions

Provides essential safety guidelines for using the PC System, including grounding, power handling, and unit mounting.

SECTION 1 PC Setup and Other Features

1-1 PC Setup

Explains operating parameters for CQM1H control, including default values and how to change them.

SECTION 2 Inner Boards

2-1 High-speed Counter Board

Describes the functions, input modes, comparison operations, and external outputs of the High-speed Counter Board.

2-2 Pulse I/O Board

Details the Pulse I/O Board's support for two pulse inputs and two pulse outputs, including input modes and interrupts.

SECTION 3 Memory Areas

3-1 Memory Area Structure

Explains the memory areas used by the CQM1H PC, including IR, Work, Controller Link status, MACRO operand, Inner Board, Analog, High-speed Counter, and EM areas.

SECTION 4 Ladder-diagram Programming

4-1 Basic Procedure

Outlines the fundamental steps for writing a program, including obtaining I/O lists and drawing ladder diagrams.

4-4 Controlling Bit Status

Details instructions for controlling individual bit status: OUTPUT, OUTPUT NOT, SET, RESET, DIFFERENTIATE UP/DOWN, KEEP.

4-6 Programming Precautions

Provides essential precautions for drawing clear ladder diagrams and inputting programs, emphasizing instruction order and TR bits.

4-7 Program Execution

Describes the CPU Unit's program scan from top to bottom, checking conditions, and executing instructions.

SECTION 5 Instruction Set

SECTION 6 Host Link Commands

6-1 Host Link Command Summary

Provides a summary table of Host Link commands available for CQM1H communications.

6-4 Command and Response Formats

Details the formats for commands issued from the host computer and responses received from the PC.

6-5 Host Link Commands

Lists and describes various Host Link commands for reading and writing data in IR, SR, LR, HR, DM, EM, and AR areas.

SECTION 7 CPU Unit Operation and Processing Time

7-1 CPU Unit Operation

Explains the overall operation flowchart of the CQM1H CPU Unit and defines cycle time.

7-2 Power Interruptions

Details the CPU Unit's behavior during power interruptions and momentary power supply failures.

7-3 Cycle Time

Explains the processes involved in a single execution cycle and their respective processing times.

SECTION 8 Troubleshooting

8-2 Programming Console Operation Errors

Lists common error messages encountered when using the Programming Console and their appropriate responses.

8-3 Programming Errors

8-5 Operating Errors

8-6 Error Log

8-7 Troubleshooting Flowcharts

Appendix A Programming Instructions

5-8 Ladder Diagram Instructions

Explains basic instructions like LOAD, AND, OR, and their combinations, including logic block instructions.

5-9 Bit Control Instructions

Covers instructions for controlling individual bit status: OUT, OUT NOT, SET, RESET, DIFU, DIFD, KEEP.

5-14 User Error Instructions: FAILURE ALARM AND RESET – FAL(06) and SEVERE FAILURE ALARM – FALS(07)

Describes instructions for outputting error numbers for operation, maintenance, and debugging, including non-fatal and fatal errors.

5-16 Timer and Counter Instructions

Details instructions for managing timers and counters, including TIM, TIMH, CNT, CNTR, TTIM, STIM, and CTBL.

5-29 Network Instructions

Explains instructions for communicating with other PCs via the Controller Link System, including SEND, RECV, and CMND.

5-30 Communications Instructions

Details instructions for serial communications, including RECEIVE (RXD), TRANSMIT (TXD), CHANGE SERIAL PORT SETUP (STUP), and PROTOCOL MACRO (PMCR).