Omron CQM1H - PROGRAM User Manual

27
Interrupt Functions Section 1-4
routine for input interrupt 0 unless it was refreshed (in this case, the Always
ON Flag, SR 25313 could be used in place of IR 00000).
Input Interrupt Mode Use the following instructions to program input interrupts using the Input Inter-
rupt Mode.
Masking of Interrupts
With the INT(89) instruction, set or clear input interrupt masks as required.
At the beginning of operation, all of the input interrupts are masked. Use
INT(89) to unmask input interrupts before using input interrupts in input inter-
rupt mode.
Clearing Masked Interrupts
If the bit corresponding to an input interrupt turns ON while masked, that input
interrupt will be saved in memory and will be executed as soon as the mask is
cleared. In order for that input interrupt not to be executed when the mask is
cleared, the interrupt must be cleared from memory.
Only one interrupt signal will be saved in memory for each interrupt number.
With the INT(89) instruction, clear the input interrupt from memory.
Reading Mask Status
With the INT(89) instruction, read the input interrupt mask status.
Counter Mode Use the following steps to program input interrupts using the Input Interrupt
Mode.
Note The SR words used in the Counter Mode (SR 244 to SR 251) all contain
binary (hexadecimal) data (not BCD).
1,2,3... 1. Write the set values for counter operation to SR words correspond to inter-
rupts 0 to 3. The set values are written between 0000 and FFFF (0 to
65,535). A value of 0000 will disable the count operation until a new value
is set and step 2, below, is repeated.
Note These SR bits are cleared at the beginning of operation, and must be
written from the program.
That maximum input signal that can be counted is 1 kHz.
(@)INT(89)
000
000
D
Make the settings with the D bits 0 to 3, which correspond to
input interrupts 0 to 3.
0: Mask cleared. (Input interrupt permitted.)
1: Mask set. (Input interrupt not permitted.)
(@)INT(89)
001
000
D
If D bits 0 to 3, which correspond to input interrupts 0 to 3, are
set to "1," then the input interrupts will be cleared from memory.
0: Input interrupt retained.
1: Input interrupt cleared.
(@)INT(89)
002
000
D
The status of the rightmost digit of the data stored in word D (bits
0 to 3) show the mask status.
0: Mask cleared. (Input interrupt permitted.)
1: Mask set. (Input interrupt not permitted.)
Interrupt Word containing counter SV
Input interrupt 0 SR 244
Input interrupt 1 SR 245
Input interrupt 2 SR 246
Input interrupt 3 SR 247

Omron CQM1H - PROGRAM Specifications

General

I/O Capacity	Up to 512 points
Power Supply	100 to 240 VAC, 50/60 Hz or 24 VDC (depending on model)
Instruction Set	Basic and advanced instructions
Operating Temperature	0 to 55°C
Program Capacity	7.2K to 15.2K steps
Communication Ports	RS-232C
Expansion Slots	Up to 3 expansion units
Type	Programmable Logic Controller (PLC)
CPU Type	RISC
Program Memory	7.2K to 15.2K steps
I/O Points	512 max
Expansion Capability	Up to 3 expansion units
Data Memory	RAM (battery backup)

Summary

PRECAUTIONS

1 Intended Audience

Specifies the target personnel for this manual, requiring knowledge of electrical systems and FA systems.

2 General Precautions

Outlines user responsibilities for operating the product according to specifications and consulting representatives for specific applications.

3 Safety Precautions

Details critical safety warnings related to I/O refreshing, touching internal components, disassembly, and power supply handling.

5 Application Precautions

Provides essential safety guidelines for using the PC System, including grounding, power handling, and unit mounting.

SECTION 1 PC Setup and Other Features

1-1 PC Setup

Explains operating parameters for CQM1H control, including default values and how to change them.

SECTION 2 Inner Boards

2-1 High-speed Counter Board

Describes the functions, input modes, comparison operations, and external outputs of the High-speed Counter Board.

2-2 Pulse I/O Board

Details the Pulse I/O Board's support for two pulse inputs and two pulse outputs, including input modes and interrupts.

SECTION 3 Memory Areas

3-1 Memory Area Structure

Explains the memory areas used by the CQM1H PC, including IR, Work, Controller Link status, MACRO operand, Inner Board, Analog, High-speed Counter, and EM areas.

SECTION 4 Ladder-diagram Programming

4-1 Basic Procedure

Outlines the fundamental steps for writing a program, including obtaining I/O lists and drawing ladder diagrams.

4-4 Controlling Bit Status

Details instructions for controlling individual bit status: OUTPUT, OUTPUT NOT, SET, RESET, DIFFERENTIATE UP/DOWN, KEEP.

4-6 Programming Precautions

Provides essential precautions for drawing clear ladder diagrams and inputting programs, emphasizing instruction order and TR bits.

4-7 Program Execution

Describes the CPU Unit's program scan from top to bottom, checking conditions, and executing instructions.

SECTION 5 Instruction Set

SECTION 6 Host Link Commands

6-1 Host Link Command Summary

Provides a summary table of Host Link commands available for CQM1H communications.

6-4 Command and Response Formats

Details the formats for commands issued from the host computer and responses received from the PC.

6-5 Host Link Commands

Lists and describes various Host Link commands for reading and writing data in IR, SR, LR, HR, DM, EM, and AR areas.

SECTION 7 CPU Unit Operation and Processing Time

7-1 CPU Unit Operation

Explains the overall operation flowchart of the CQM1H CPU Unit and defines cycle time.

7-2 Power Interruptions

Details the CPU Unit's behavior during power interruptions and momentary power supply failures.

7-3 Cycle Time

Explains the processes involved in a single execution cycle and their respective processing times.

SECTION 8 Troubleshooting

8-2 Programming Console Operation Errors

Lists common error messages encountered when using the Programming Console and their appropriate responses.

8-3 Programming Errors

8-5 Operating Errors

8-6 Error Log

8-7 Troubleshooting Flowcharts

Appendix A Programming Instructions

5-8 Ladder Diagram Instructions

Explains basic instructions like LOAD, AND, OR, and their combinations, including logic block instructions.

5-9 Bit Control Instructions

Covers instructions for controlling individual bit status: OUT, OUT NOT, SET, RESET, DIFU, DIFD, KEEP.

5-14 User Error Instructions: FAILURE ALARM AND RESET – FAL(06) and SEVERE FAILURE ALARM – FALS(07)

Describes instructions for outputting error numbers for operation, maintenance, and debugging, including non-fatal and fatal errors.

5-16 Timer and Counter Instructions

Details instructions for managing timers and counters, including TIM, TIMH, CNT, CNTR, TTIM, STIM, and CTBL.

5-29 Network Instructions

Explains instructions for communicating with other PCs via the Controller Link System, including SEND, RECV, and CMND.

5-30 Communications Instructions

Details instructions for serial communications, including RECEIVE (RXD), TRANSMIT (TXD), CHANGE SERIAL PORT SETUP (STUP), and PROTOCOL MACRO (PMCR).