Panasonic FP0 - Page 231

Specifications
FP0
12 − 13
12.4 FP0−SL1 S−LINK Address
12.4 FP0−SL1 S−LINK Address
I/O ad-
dress
S−LINK address I/O ad-
dress
S−LINK address I/O ad-
dress
S−LINK address I/O ad-
dress
S−LINK address
dress
input
(X)
Deci-
mal
Hexade-
cimal
dress
input
(X)
Deci-
mal
Hexade-
cimal
dress
input
(X)
Deci-
mal
Hexade-
cimal
dress
input
(X)
Deci-
mal
Hexade-
cimal
X80 0 0 X90 16 10 X100 32 20 X110 48 30
X81 1 1 X91 17 11 X101 33 21 X111 49 31
X82 2 2 X92 18 12 X102 34 22 X112 50 32
X83 3 3 X93 19 13 X103 35 23 X113 51 33
X84 4 4 X94 20 14 X104 36 24 X114 52 34
X85 5 5 X95 21 15 X105 37 25 X115 53 35
X86 6 6 X96 22 16 X106 38 26 X116 54 36
X87 7 7 X97 23 17 X107 39 27 X117 55 37
X88 8 8 X98 24 18 X108 40 28 X118 56 38
X89 9 9 X99 25 19 X109 41 29 X119 57 39
X8A 10 A X9A 26 1A X10A 42 2A X11A 58 3A
X8B 11 B X9B 27 1B X10B 43 2B X11B 59 3B
X8C 12 C X9C 28 1C X10C 44 2C X11C 60 3C
X8D 13 D X9D 29 1D X10D 45 2D X11D 61 3D
X8E 14 E X9E 30 1E X10E 46 2E X11E 62 3E
X8F 15 F X9F 31 1F X10F 47 2F X11F 63 3F
I/O ad-
dress
S−LINK address I/O ad-
dress
S−LINK address I/O ad-
dress
S−LINK address I/O ad-
dress
S−LINK address
dress
input
(Y)
Deci-
mal
Hexade-
cimal
dress
input
(Y)
Deci-
mal
Hexade-
cimal
dress
input
(Y)
Deci-
mal
Hexade-
cimal
dress
input
(Y)
Deci-
mal
Hexade-
cimal
Y80 64 40 Y90 80 50 Y100 96 60 Y110 112 70
Y81 65 41 Y91 81 51 Y101 97 61 Y111 113 71
Y82 66 42 Y92 82 52 Y102 98 62 Y112 114 72
Y83 67 43 Y93 83 53 Y103 99 63 Y113 115 73
Y84 68 44 Y94 84 54 Y104 100 64 Y114 116 74
Y85 69 45 Y95 85 55 Y105 101 65 Y115 117 75
Y86 70 46 Y96 86 56 Y106 102 66 Y116 118 76
Y87 71 47 Y97 87 57 Y107 103 67 Y117 119 77
Y88 72 48 Y98 88 58 Y108 104 68 Y118 120 78
Y89 73 49 Y99 89 59 Y109 105 69 Y119 121 79
Y8A 74 4A Y9A 90 5A Y10A 106 6A Y11A 122 7A
Y8B 75 4B Y9B 91 5B Y10B 107 6B Y11B 123 7B
Y8C 76 4C Y9C 92 5C Y10C 108 6C Y11C 124 7C
Y8D 77 4D Y9D 93 5D Y10D 109 6D Y11D 125 7D
Y8E 78 4E Y9E 94 5E Y10E 110 6E Y11E 126 7E
Y8F 79 4F Y9F 95 5F Y10F 111 6F Y11F 127 7F