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RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE

R01UH0368EJ0210 Rev.2.10 149

Dec 10, 2015

Table 3-5. SFR List (3/4)

Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset

1-bit 8-bit 16-bit

FFF70H Timer data register 10 TDR10 R/W – –



0000H

FFF71H

FFF72H Timer data register 11 TDR11L TDR11 R/W –

 

00H

FFF73H TDR11H –



00H

FFF74H Timer data register 12 TDR12 R/W – –



0000H

FFF75H

FFF76H Timer data register 13 TDR13L TDR13 R/W –

 

00H

FFF77H TDR13H

–



00H

FFF78H Timer data register 14 TDR14 R/W – –



0000H

FFF79H

FFF7AH Timer data register 15 TDR15 R/W – –



0000H

FFF7BH

FFF7CH Timer data register 16 TDR16 R/W – –



0000H

FFF7DH

FFF7EH Timer data register 17 TDR17

R/W – –



0000H

FFF7FH

FFF92H Second count register SEC

R/W –



– 00H

FFF93H Minute count register MIN

R/W –



– 00H

FFF94H Hour count register HOUR R/W –



– 12H

Note 1

FFF95H Week count register WEEK

R/W –



– 00H

FFF96H Day count register DAY

R/W –



– 01H

FFF97H Month count register MONTH

R/W –



– 01H

FFF98H Year count register YEAR R/W –



– 00H

FFF99H Watch error correction register SUBCUD

R/W –



– 00H

FFF9AH Alarm minute register ALARMWM R/W –



– 00H

FFF9BH Alarm hour register ALARMWH R/W –



– 12H

FFF9CH Alarm week register ALARMWW R/W –



– 00H

FFF9DH Real-time clock control register 0 RTCC0 R/W

 

– 00H

FFF9EH Real-time clock control register 1 RTCC1 R/W

 

– 00H

FFFA0H Clock operation mode control register CMC R/W –



– 00H

FFFA1H Clock operation status control register CSC R/W

 

– C0H

FFFA2H

Oscillation stabilization time counter status

OSTC R

 

– 00H

FFFA3H Oscillation stabilization time select register OSTS R/W –



– 07H

FFFA4H System clock control register CKC R/W

 

– 00H

FFFA5H Clock output select register 0 CKS0 R/W

 

– 00H

FFFA8H Reset control flag register RESF R –



–

Undefined

Note 2

FFFA9H Voltage detection register LVIM R/W

 

– 00H

Note 3

Notes 1. The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1

after reset.

2. The reset value of the RESF register varies depending on the reset source.

3. The reset value of the LVIM register varies depending on the reset source.

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English

Renesas RL78/D1A User Manual

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