RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 150
Dec 10, 2015
Table 3-5. SFR List (4/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range Undefined
1-bit 8-bit 16-bit
FFFAAH Voltage detection level register LVIS R/W
 
–
00H/01H/
81H
Note 1
FFFABH Watchdog timer enable register WDTE R/W –

–
1AH/
9AH
Note 2
FFFACH CRC input register CRCIN R/W –

– 00H
FFFD0H Interrupt request flag register 2L IF2L IF2 R/W
  
00H
FFFD1H Interrupt request flag register 2H IF2H R/W
 
00H
FFFD2H Interrupt request flag register 3L IF3L R/W
 
– 00H
FFFD4H Interrupt mask flag register 2L MK2L MK2 R/W
  
FFH
FFFD5H Interrupt mask flag register 2H MK2H R/W
 
FFH
FFFD6H Interrupt mask flag register 3L MK3L R/W
 
– FFH
FFFD8H Priority specification flag register 02L PR02L PR02 R/W
  
FFH
FFFD9H Priority specification flag register 02H PR02H R/W
 
FFH
FFFDAH Priority specification flag register 03L PR03L R/W
 
– FFH
FFFDCH Priority specification flag register 12L PR12L PR12 R/W
  
FFH
FFFDDH Priority specification flag register 12H PR12H R/W
 
FFH
FFFDEH Priority specification flag register 13L PR13L R/W
 
– FFH
FFFE0H Interrupt request flag register 0L IF0L IF0 R/W
  
00H
FFFE1H Interrupt request flag register 0H IF0H R/W
 
00H
FFFE2H Interrupt request flag register 1L IF1L IF1 R/W
  
00H
FFFE3H Interrupt request flag register 1H IF1H R/W
 
00H
FFFE4H Interrupt mask flag register 0L MK0L MK0 R/W
  
FFH
FFFE5H Interrupt mask flag register 0H MK0H R/W
 
FFH
FFFE6H Interrupt mask flag register 1L MK1L MK1 R/W
  
FFH
FFFE7H Interrupt mask flag register 1H MK1H R/W
 
FFH
FFFE8H Priority specification flag register 00L PR00L PR00 R/W
  
FFH
FFFE9H Priority specification flag register 00H PR00H R/W
 
FFH
FFFEAH Priority specification flag register 01L PR01L PR01 R/W
  
FFH
FFFEBH Priority specification flag register 01H PR01H R/W
 
FFH
FFFECH Priority specification flag register 10L PR10L PR10 R/W
  
FFH
FFFEDH Priority specification flag register 10H PR10H R/W
 
FFH
FFFEEH Priority specification flag register 11L PR11L PR11 R/W
  
FFH
FFFEFH Priority specification flag register 11H PR11H R/W
 
FFH
FFFF0H Multiply and accumulation register (L) MACRL R/W – –

0000H
FFFF1H
FFFF2H Multiply and accumulation register (H) MACRH R/W – –

0000H
FFFF3H
FFFFEH Processor mode control register PMC R/W
 
– 00H
Notes 1. The reset value of the LVIS register varies depending on the reset source and the setting of the option byte.
2. The reset value of the WDTE register is determined by the setting of the option byte.
Remark For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.
To Next Page
Loading...
Need help?
General
