RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 171
Dec 10, 2015
Table 3-6. Extended SFR (2nd SFR) List (20/32)
Address Special Function Register (2nd SFR) Name Symbol R/W Manipulable Bit Range
After
reset
1-bit 8-bit 16-bit
F0444H CAN receive rule entry register 13CL
Note 1
GAFLPL13L GAFLPL13 R/W – √ √ 0000H
F0445H GAFLPL13H – √
F0444H CAN receive buffer register 10BL
Note 2
RMTS10L RMTS10 R – √ √ 0000H
F0445H RMTS10H – √
F0446H CAN receive rule entry register 13CH
Note 1
GAFLPH13L GAFLPH13 R/W – √ √ 0000H
F0447H GAFLPH13H – √
F0446H CAN receive buffer register 10BH
Note 2
RMPTR10L RMPTR10 R – √ √ 0000H
F0447H RMPTR10H – √
F0448H CAN receive rule entry register 14AL
Note 1
GAFLIDL14L GAFLIDL14 R/W – √ √ 0000H
F0449H GAFLIDL14H – √
F0448H CAN receive buffer register 10CL
Note 2
RMDF010L RMDF010 R – √ √ 0000H
F0449H RMDF010H – √
F044AH CAN receive rule entry register 14AH
Note 1
GAFLIDH14L GAFLIDH14 R/W – √ √ 0000H
F044BH GAFLIDH14H – √
F044AH CAN receive buffer register 10CH
Note 2
RMDF110L RMDF110 R – √ √ 0000H
F044BH RMDF110H – √
F044CH CAN receive rule entry register 14BL
Note 1
GAFLML14L GAFLML14 R/W – √ √ 0000H
F044DH GAFLML14H – √
F044CH CAN receive buffer register 10DL
Note 2
RMDF210L RMDF210 R – √ √ 0000H
F044DH RMDF210H – √
F044EH CAN receive rule entry register 14BH
Note 1
GAFLMH14L GAFLMH14 R/W – √ √ 0000H
F044FH GAFLMH14H – √
F044EH CAN receive buffer register 10DH
Note 2
RMDF310L RMDF310 R – √ √ 0000H
F044FH RMDF310H – √
F0450H CAN receive rule entry register 14CL
Note 1
GAFLPL14L GAFLPL14 R/W – √ √ 0000H
F0451H GAFLPL14H – √
F0450H CAN receive buffer register 11AL
Note 2
RMIDL11L RMIDL11 R – √ √ 0000H
F0451H RMIDL11H – √
F0452H CAN receive rule entry register 14CH
Note 1
GAFLPH14L GAFLPH14 R/W – √ √ 0000H
F0453H GAFLPH14H – √
F0452H CAN receive buffer register 11AH
Note 2
RMIDH11L RMIDH11 R – √ √ 0000H
F0453H RMIDH11H – √
F0454H CAN receive rule entry register 15AL
Note 1
GAFLIDL15L GAFLIDL15 R/W – √ √ 0000H
F0455H GAFLIDL15H – √
F0454H CAN receive buffer register 11BL
Note 2
RMTS11L RMTS11 R – √ √ 0000H
F0455H RMTS11H – √
F0456H CAN receive rule entry register 15AH
Note 1
GAFLIDH15L GAFLIDH15 R/W – √ √ 0000H
F0457H GAFLIDH15H – √
F0456H CAN receive buffer register 11BH
Note 2
RMPTR11L RMPTR11 R – √ √ 0000H
F0457H RMPTR11H – √
F0458H CAN receive rule entry register 15BL
Note 1
GAFLML15L GAFLML15 R/W – √ √ 0000H
F0459H GAFLML15H – √
F0458H CAN receive buffer register 11CL
Note 2
RMDF011L RMDF011 R – √ √ 0000H
F0459H RMDF011H – √
Notes 1. These registers are allocated to the RAM window 0 for the CAN module (receive rule and CAN RAM test register).
When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to the RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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