RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 620
Dec 10, 2015
(4) Pulse Output Forced Cutoff
In the PWM function, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, the TRDIOji
output pin (i = 0 or 1, j = A, B, C, or D) can be forcibly set to an I/O port by the INTP0 pin input, and pulse output can
be cut off.
The pins used for output in these functions or modes can function as the output pin of timer RD when the
corresponding bit in the TRDOER1 register is set to 0 (timer RD output enabled). When the TRDPTO bit in the
TRDOER2 register is 1 (pulse output forced cutoff signal input INTP0 enabled), the output pin used as a timer RD
output port outputs the output value set by the DFCK1, DFCK0, PENB1, PENB0, DFD, DFC, DFB, or DFA bit in the
TRDDF0 or TRDDF1 register.
Make the following settings to use this function:
ï‚· Set the pin state when the pulse output is forcibly cut off (high impedance, low output, or high output) using TRDDFi.
ï‚· Refer to 8.3.1 (5) Event Input from Event Link Controller (ELC) for details on pulse forced cutoff by ELC
Note
event input.
ï‚· When pulse output is forcibly cut out, the TRDSHUTS bit in the TRDOER2 register is set to 1. To suspend the
forced cutoff of the pulse output, set the TRDSHUTS bit to 0 while the count is stopped (TSTARTi = 0).
ï‚· Set the TRDPTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INTP0 enabled).
Note The ELC is only available in the RL78/F14.
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