Renesas RL78/F14 User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1119
Dec 10, 2015
(11) LIN Break Field Configuration Register/UART Configuration Register (LBFCn)
Address: F06C9H
7 6 5 4 3 2 1 0
— — BDT[1:0]
BLT[3:0]
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
3 to 0 BLT[3:0] Transmission Break (Low) Width Select
b3 b0
0 0 0 0: 13 Tbits
0 0 0 1: 14 Tbits
0 0 1 0: 15 Tbits

1 1 1 0: 27 Tbits
1 1 1 1: 28 Tbits
R/W
5, 4 BDT[1:0] Transmission Break Delimiter (High)
Width Select
b5 b4
0 0: 1 Tbit
0 1: 2 Tbits
1 0: 3 Tbits
1 1: 4 Tbits
R/W
6 — Reserved This bit is always read as 0. The write value should always
be 0.
R/W
7 — Reserved This bit is always read as 0. The write value should always
be 0.
R/W
Set the LBFCn register when the OMM0 bit in the LMSTn register is 0 (LIN reset mode).
Some combinations of the set values result in the length of a frame exceeding the frame timeout time. Set the appropriate
values in this register.
BLT[3:0] bits (transmission break (low) width select bits)
The BLT bits set the break (low) width of the transmission frame header.
13 Tbits to 28 Tbits can be set.
BDT bits (transmission break delimiter (high) width select bits)
The BDT bits set the break delimiter (high) width of the transmission frame header field.
1 Tbit to 4 Tbits can be set.

Renesas RL78/F14 Specifications

General

Brand	Renesas
Model	RL78/F14
Category	Computer Hardware
Language	English