Renesas RL78/F14 User Manual

RL78/F13, F14 CHAPTER 24 RESET FUNCTION
R01UH0368EJ0210 Rev.2.10 1543
Dec 10, 2015
Figure 24-2. Timing of Reset by RESET Input
Figure 24-3. Timing of Reset by Watchdog Timer Overflow, Execution of Illegal Instruction, Clock Monitor, or
Illegal-Memory Access
(Notes, Caution, and Remark are listed on the next page.)
Delay
Hi-Z
Normal operationCPU status
Normal operation
(high-speed on-chip oscillator clock)
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Note 1
High-speed system clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Starting X1 oscillation is specified by software.
Reset processing
Wait for oscillation
accuracy stabilization
Reset period
Note 2
Normal operation
Reset period
(oscillation stop)
CPU status
Watchdog timer overflow/
execution of illegal instruction/
clock monitor/
illegal memory access
Internal reset signal
Hi-Z
Note 1
High-speed system clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Starting X1 oscillation is specified by software.
Normal operation
(high-speed on-chip oscillator clock)
Wait for oscillation
accuracy stabilization
Reset processing
Port pin
(except P130)
Port pin
(P130)
0.0511 ms (typ.)
0.0701 ms (max.)

Renesas RL78/F14 Specifications

General

Brand	Renesas
Model	RL78/F14
Category	Computer Hardware
Language	English