RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 645
Dec 10, 2015
Table 8-19. PWM3 Mode Specifications
Item Specification
Count sources
Note
fCLK, fPLL, fIH, fSUB, fIL
Count operations The TRD0 register is incremented (the TRD1 register is not used).
PWM waveform PWM period: 1/fk × (m + 1)
Active level width of TRDIOA0 output: 1/fk × (m - n)
Active level width of TRDIOB0 output: 1/fk × (p - q)
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRA1 register
p: Value set in the TRDGRB0 register
q: Value set in the TRDGRB1 register
Count start condition 1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
Count stop conditions
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR register when the
CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds the output level before the count stops.
• When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at compare
match with the TRDGRA0 register.
The PWM output pin holds the level after output change by compare match.
Interrupt request generation timing • Compare match (content of the TRDi register matches content of the TRDGRji
register)
• TRD0 register overflow
TRDIOA0, TRDIOB0 pin function PWM output
TRDIOA0, TRDIOD0, and
TRDIOA1 to TRDIOD1 pin function
I/O port
INTP0 pin function
Pulse output forced cutoff signal input (port or INTP0 interrupt input)
Read from timer The count value can be read by reading the TRD0 register.
Write to timer The value can be written to the TRD0 register.
Selectable functions • Pulse output forced cutoff signal input (see 8. 3. 1 (4) Pulse Output Forced Cutoff)
• Active level selectable for each pin.
• Buffer operation (see 8. 3. 1 (2) Buffer Operation)
Note When selecting the count source for the timer RD, set the same clock source as the count source for fCLK before
setting bit 4 (TRD0EN) in the peripheral enable register 1 (PER1).
Remark i = 0 or 1, j = A, B, C, or D
m + 1
p - q
m - n
n + 1
p + 1
q + 1
TRDIOA0 output
TRDIOB0 output
(When high is selected as the active level )
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