Renesas RL78/F14 - Page 751

RL78/F13, F14 CHAPTER 12 A/D CONVERTER
R01UH0368EJ0210 Rev.2.10 719
Dec 10, 2015
Figure 12-8. ADRCK Bit Interrupt Signal Generation Range
Remark If INTAD does not occur, the A/D conversion result is not stored in the ADCR or ADCRH register.
1111111111
0000000000
ADCR register value
(A/D conversion result)
<1>
(ADLL ≤ ADCR ≤ ADUL)
<2>
(ADCR < ADLL)
<3>
(ADUL < ADCR)
ADUL register setting
INTAD is generated
when ADRCK = 0.
INTAD is generated
when ADRCK = 1.
INTAD is generated
when ADRCK = 1.
ADLL register setting