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Rohde & Schwarz RTM2032 - I²C (Option R&S RTM-K1); The I²C Protocol

Rohde & Schwarz RTM2032
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Protocol Analysis
R&S
®
RTM20xx
165User Manual 1317.4726.02 ─ 01
BUS<b>:SPI:FRAME<n>:WORD<o>:STARt? on page 384
BUS<b>:SPI:FRAME<n>:WORD<o>:STOP? on page 384
BUS<b>:SPI:FRAME<n>:WORD<o>:MOSI? on page 385
BUS<b>:SPI:FRAME<n>:WORD<o>:MISO? on page 385
11.3 I²C (Option R&S RTM-K1)
The Inter-Integrated Circuit is a simple, lowbandwidth, low-speed protocol used for com-
munication between on-board devices, for example, in LCD and LED drivers, RAM,
EEPROM, and others.
11.3.1 The I²C Protocol
This chapter provides an overview of protocol characteristics, data format, address types
and trigger possibilities. For detailed information, read the "I2C-bus specification and user
manual" available on the NXP manuals web page at http://www.nxp.com/.
I²C characteristics
Main characteristics of I²C are:
Two-wire design: serial clock (SCL) and serial data (SDA) lines
Master-slave communication: the master generates the clock and addresses the
slaves. Slaves receive the address and the clock. Both master and slaves can trans-
mit and receive data.
Addressing scheme: each slave device is addressable by a unique address. Multiple
slave devices can be linked together and can be addressed by the same master.
Read/write bit: specifies if the master will read (=1) or write (=0) the data.
Acknowledge: takes place after every byte. The receiver of the address or data sends
the acknowledge bit to the transmitter.
The R&S RTM supports all operating speed modes: high-speed, fast mode plus, fast
mode, and standard mode.
Data transfer
The format of a simple I²C message (frame) with 7 bit addressing consists of the following
parts:
Start condition: a falling slope on SDA while SCL is high
7-bit address of the slave device that either will be written to or read from
R/W bit: specifies if the data will be written to or read from the slave
ACKnowledge bits: is issued by the receiver of the previous byte if the transfer was
successful
Exception: At read access, the master terminates the data transmission with a NACK
bit after the last byte.
Data: a number of data bytes with an ACK bit after every byte
I²C (Option R&S RTM-K1)

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