Samsung HS40 - Page 184

5 – 16 HS40 Service Manual
[Figure 5.9 Back End Board Block Diagram]
TYPE 6 PC
LVD S
P EG
US B3.
0
PCI
e
LAN
SA TA
SO UN D
US B
PC Ie
C onf i g
PCI CLK
SPI
P owe r
DD I
ED ID
DD I
P owe r
125p Press fit
CN23
125p Press fit
CN1
110p Press fit
CN25
FPGA
+방열
판
FPGA
U26
8311
U32
CPLD
U53
60p Press fit
CN2
Clock
PCIs-
Filter
Re-
Driver
Buffer
U25
U6
MDIN
U52
Diagnostic
U10
5V_D
U17
3.3V_D
U9
1.5V_D
U20
2.5V_D
Filter
POWER
U2
2
N5
V
U2
1
3.3
SB
U3
VIDEO
CN19
CR2032
BAT1
Motor
SODIMM
CN14
Insert
Clock -
LVDS
HOS T
RX
HOS T
TX
BF CLK /
PRT
LMK
Con trol
SPI I/O
BF
F PGA
Con fig
BF SUM
RX0
BF SUM
RX1
34
33
32
12
13
14
15
16
17
18
CPLD
0
1
2
3
[Figure 5.10 Back End Layout]