Video Option
CH2
AC
Clamp
(Diagram 26)
From Composite
Sync
to
Trigger Signal
(Diagram 27)
3-38
The
COMPSYNC
and
the COMPSYNC_o signals are
used
to create sam-
pling pulses for
the
TRIGGER
BACKPORCH CLAMP
and
the SYNC TIP
CLAMP.
The
COMPSYNC signal samples the
output
of the fixed gain amplifier
during the sync pulse
and
controls the gain of the
input
stage to obtain a
signal with constant amplitude.
The COMPSYNC_0 signal samples the
output
of the fixed gain amplifier
after
the
sync pulse during black level
and
controls
the
offset
of
the
fixed
gain amplifier.
After the sync pulse, during black level, U2605 samples
the
offset
of
the
input
signal. U2605D/Q2605 form a sample and hold amplifier circuit.
The
output of this sample
and
hold
amplifier is
an
amplified, calibrated
signal and further passed
on
to the
CH2
position control circuit.
An
composite video
input
signal
that
is polluted by tilt or
hum
from a
power
line ( 50 or 60 Hz ) will
be
displayed stable
on
the
screen.
(See Timing Diagram Figure 3-9).
The composite sync signal is used to synchronize a PLL (U2705) via C2711
and
a pulse stretcher (Q2702, Q2703 and U2715).
The
PLL runs at twice the
frequency of the horizontal sync pulses
in
the
composite sync signal
(2XH_0).
U2704B divides 2XH_0 to HORIZCLK_0 for the
PLL
and
HCLK.
U2704A creates
DL
Y'DCLK
which
has a delay of 90 degrees from
HCLK.
If TV
_EN_0
is valid, ALL_LINES is valid,
and
UNLOCKED is
not
valid (so
U2704A is running), then the combinatorial logic inside U2708 creates a
trigger pulse on every line sync pulse. The pulses are created from
the
output
of the pulse stretcher ( CMPSS
).
Some video systems have
no
line sync pulses during vertical sync.
In
those
systems, the
HCLK
is used to create the trigger pulse, during vertical sync,
after a small delay. The delay is necessary to prevent trigger jitter.
The
HCLK
is
not
as stable as the CMPSS signal.
U2701A retrieves
the
VERT
sync signal from the composite sync signal.
U2701 detects
if
the
TV system
under
test is interlaced or not. If the system
is interlaced, U2703A generates a
FIELD
pulse during field 1. If the system
is
not
interlaced, U2702B generates a
FIELD
pulse at
the
beginning of each
field.
Revised 3/93
Theory
of
Operation
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