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Command Strobe/CSMA-CA Processor
Step3: For packet sniffing, the packet sniffer module must be enabled in the MDMTEST1 register.
23.14 Command Strobe/CSMA-CA Processor
The command strobe/CSMA-CA processor (CSP) provides the control interface between the CPU and the
radio.
The CSP interfaces with the CPU through the SFR register RFST and the XREG registers CSPX, CSPY,
CSPZ, CSPT, CSPSTAT, CSPCTRL, and CSPPROG<n> (where n is in the range 0 to 23). The CSP produces
interrupt requests to the CPU. In addition, the CSP interfaces with the MAC Timer by observing MAC
Timer events.
The CSP allows the CPU to issue command strobes to the radio, thus controlling the operation of the
radio.
The CSP has two modes of operation, which are described as follows.
• Immediate command strobe execution
• Program execution
Immediate command strobes are written as Immediate Command Strobe instructions to the CSP, which
are issued instantly to the radio module. The Immediate Command Strobe instructions are also used to
control the CSP. The Immediate Command Strobe instructions are described in Section 23.14.8.
Program execution mode means that the CSP executes a sequence of instructions, comprising a short
user-defined program, from a program memory or instruction memory. The available instructions are from
a set of 20 instructions. The instruction set is defined in Section 23.14.8. The required program is first
loaded into the CSP by the CPU, and then the CPU instructs the CSP to start executing the program.
The program execution mode, together with the MAC Timer, allows the CSP to automate CSMA-CA
algorithms and thus act as a coprocessor for the CPU.
The operation of the CSP is described in detail in the following sections. The command strobes and other
instructions supported by the CSP are given in Section 23.14.9.
RFST (0xE1) – RF CSMA-CA/Strobe Processor
Bit Name Reset R/W Description
7:0
INSTR[7:0]
0xD0 R/W Data written to this register is written to the CSP instruction memory. Reading this register
returns the CSP instruction currently being executed.
23.14.1 Instruction Memory
The CSP executes single-byte program instructions which are read from a 24-byte instruction memory.
Writes to the instruction memory are sequential, written through SFR register RFST. An instruction write
pointer is maintained within the CSP to hold the location within the instruction memory where the next
instruction written to RFST is to be stored. For debugging purposes, the program currently loaded into the
CSP can be read from the XREG registers CSPPROG<n>. Following a reset, the write pointer is reset to
location 0. During each RFST register write, the write pointer is incremented by 1 until the end of memory
is reached, at which time the write pointer stops incrementing. The first instruction written to RFST is
stored in location 0, the location where program execution starts. Thus, a complete 24-instruction program
is written to the instruction memory by writing each instruction in the desired order to the RFST register.
The write pointer can be reset to 0 by writing the immediate command strobe instruction ISSTOP. In
addition, the write pointer is reset to 0 when the command strobe SSTOP is executed in a program.
Following a reset, the instruction memory is filled with SNOP (No Operation) instructions (opcode value
0xC0). The immediate strobe ISCLEAR clears the instruction memory, filling it with SNOP instructions.
While the CSP is executing a program, there must be no attempts to write instructions to the instruction
memory by writing to RFST. Failure to observe this rule can lead to incorrect program execution and
corrupt instruction memory contents. However, Immediate Command Strobe instructions may be written to
RFST (see Section 23.14.3).
249
SWRU191C–April 2009–Revised January 2012 CC253x Radio
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