Command Strobe/CSMA-CA Processor
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CSPSTAT (0x61E1) – CSP Status Register
Bit Name Reset R/W Description
7:6 — 00 R0 Reserved. Read as 0
5
CSP_RUNNING
0 R 1: CSP is running.
0: CSP is idle.
4:0
CSP_PC
0 0000 R CSP program counter
CSPX (0x61E2) – CSP X Register
Bit Name Reset R/W Description
7:0
CSPX
0x00 R/W CSP X data register. Used by CSP instructions WAITX, RANDXY, INCX, DECX,
and conditional instructions
CSPY (0x61E3) – CSP Y Register
Bit Name Reset R/W Description
7:0
CSPY
0x00 R/W CSP Y data register. Used by CSP instructions RANDXY, INCY, DECY, and
conditional instructions
CSPZ (0x61E4) – CSP Z Register
Bit Name Reset R/W Description
7:0
CSPZ
0x00 R/W CSP Z data register. Used by CSP instructions INCZ, DECZ, and conditional
instructions
CSPT (0x61E5) – CSP T Register
Bit Name Reset R/W Description
7:0
CSPT
0xFF R/W CSP T data register. Content is decremented each time the MAC Timer
overflows while the CSP program is running. The SCP program stops when
decremented to 0. Setting CSPT = 0xFF prevents the register from being
decremented.
23.14.8 Instruction Set Summary
This section gives an overview of the instruction set. This is intended as a summary and definition of
instruction opcodes. See Section 23.14.9 for a description of each instruction. Each instruction consists of
one byte, which is written to the RFST register to be stored in the instruction memory.
The Immediate Strobe instructions (ISxxx) are not used in a program. When these instructions are written
to the RFST register, they are executed immediately. If the CSP is already executing a program, the
current instruction is delayed until the immediate strobe instruction has completed.
For undefined opcodes, the behavior of the CSP is defined as a no-operation strobe command (SNOP).
252
CC253x Radio SWRU191C–April 2009–Revised January 2012
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