UEi RACKtangle DNR-12-1G Series User Manual

DNR-X-1G Series RACKtangle and HalfRACK Systems
Chapter 2 20
The DNR-12-1G Series RACKtangle System
October 2018 www.ueidaq.com
508.921.4600
© Copyright 2018
United Electronic Industries, Inc.
The input current and all output voltages, including the +2.5, +3.3, and +24 VDC
from the NIC module, plus signals from the two temperature sensors mounted
within the enclosure, are input to a 24-bit delta-sigma A/D converter. Except for
Vin, the voltage sources use 1:23.1 dividers on the front end. Vin uses a 1:45.3
divider.
Figure 2-16 shows the interaction of modules within a DNR-12 enclosure when
the DNR-BUFFER module is used.
Figure 2-16. Functional Block Diagram of DNR-12 Enclosure
As shown above, the I/O slots are divided into two groups: 0 to 5 and 6 to 0xB.
0xC for the DC Power Module is included with the 0 to 5 group. The DNR-
BUFFER board is located at the center of the enclosure, which is also at the
center point of the ADDR/CTRL bus. The DNR-CPU-1000 module is also
located at the center of the enclosure and the center of the data bus to minimize
bus delays. The CPU addresses I/O Boards and transmits clock ticks through
the Buffer Board, which controls the Addr/Ctrl and clock lines to the modules.
Temperature sensors monitor temperatures within the enclosure above the
DNR-POWER-DC module and the DNR-CPU module.
CPU/NIC
PULLUPS
SLOTS
6...B
SLOTS
0..5, C
PWR
ADDR/CTRL
CLOCKS
TEMP1
TEMP0
2.5V
3.3V, 24V
1.2V AND 1.5V
2.5V,3.3V
ADDR/CTRL
CLOCKS
6
6
DNR-BUFFER/
CLOCK DIST.
DATA BUS
DNR-POWER-DC
PULLUPS
I/O
I/O

UEi RACKtangle DNR-12-1G Series Specifications

General

Brand	UEi
Model	RACKtangle DNR-12-1G Series
Category	Network Hardware
Language	English