DNR-X-1G Series RACKtangle and HalfRACK Systems
Chapter 4 62
Installation and Configuration
October 2018 www.ueidaq.com
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/* state flags */
#define STS_STATE_TS_SH (8)
#define STS_STATE_TS_SH_INS(S,TS,MD)
((S & 0xffff00f0)|((TS<<8) & 0xff00)|(MD&0xf))
#define STS_STATE_STICKY (0)
The second word describes the status of the board. It is written when the board
enters initialization mode and remains unchanged until the next reboot.
STS_POST_SDCARD_FAILED, STS_POST_DC24 and STS_POST_DCCORE can
be changed during operation if the corresponding failure occurs.
/* POST status flags */
#define STS_POST_MEM_FAIL (1L<<0) // Memory test failed
#define STS_POST_EEPROM_FAIL (1L<<1) // EEPROM read failed
#define STS_POST_LAYER_FAILED (1L<<2) // board failure
#define STS_POST_FLASH_FAILED (1L<<3) // Flash checksum error
#define STS_POST_SDCARD_FAILED (1L<<4) // SD card is not present
#define STS_POST_DC24 (1L<<5) // DC->24 board failed
#define STS_POST_DCCORE (1L<<6) // Core voltage problem
#define STS_POST_BUSTEST_FAILED (1L<<7) // Bus test failed (hwtest.c)
#define STS_POST_BUSFAIL_DATA (1L<<8) // Bus test failed on data tst
#define STS_POST_BUSFAIL_ADDR (1L<<9) // Bus test failed on addr tst
#define STS_POST_OVERHEAT (1L<<10) // Overheat detected
#define STS_POST_STICKY (STS_POST_MEM_FAIL|STS_POST_BUSTEST_FAILED|
STS_POST_BUSFAIL_DATA|STS_POST_BUSFAIL_ADDR)
The third word contains the logic status flags. They are read and assembled
from the various registers of the common board interface (CLI) upon request.
Not all boards implement full functionality and boards operating normally should
not show any flags set.
/*logic status flags */
#define STS_LOGIC_DC_OOR (1UL<<0) // DC/DC out of range (IOM
//also)
#define STS_LOGIC_DC_FAILED (1UL<<1) // DC/DC failed (IOM also)
#define STS_LOGIC_TRIG_START (1UL<<2) // Trigger event started
// (IOM also)
#define STS_LOGIC_TRIG_STOP (1UL<<3) // Trigger event stopped
// (IOM also)
#define STS_LOGIC_CL0_NOT_RUNNING (1UL<<4) // Output channel list not
// running
#define STS_LOGIC_CLI_NOT_RUNNING (1UL<<5) // Input channel list not
// running
#define STS_LOGIC_CVCLK_CL0_ERR (1UL<<6) // CV clock error for CL0
#define STS_LOGIC_CVCLK_CLI_ERR (1UL<<7) // CV clock error for CLI
#define STS_LOGIC_CLCLK_CL0_ERR (1UL<<8) // CL clock error for CL0
#define STS_LOGIC_CVCLK_CLI_ERR (1UL<<9) // CL clock error for CLI
#define STS_LOGIC_NO_REPORTING (1UL<<31) // Installed logic does not
// support error reporting
#define STS_LOGIC_STICKY (STS_LOGIC_NO_REPORTING)