Chapter 4 INTERFACE SETTINGS
125
[1] MODE0 ×4 Mode (Quad Link ) (Non Dividing Mode)
Using channels 1, 2, 3 and 4, the image is output under the pixel assignment given below without splitting the
screen.
Given here as an example of the resolution is 1920 × 1080, the dot clock frequency is 592 MHz with the 10 bits
output.
The ×4 mode is an output mode designed for the inspection of FPD which support the Full HD 240 Hz output. By
connecting the output of the VG generator to the IA-1540 (iTMDS-LVDS converter box) and by halving the output in
the converter box,
The explanation concerns the signals of the four channels output from the VG generator. For an explanation
concerning an 8-channel output from LVDS, refer to section “4.13.3 Data transfer systems (V-By-One HS).”
D 0 D 4 D 8 D 12
・・・
・・・
D 1904 D 1908 D 1912 D 1916
CLK
148MHz
1CH
2CH
3CH
4CH
D 3 D 7 D 11 D 15
・・・
D 1907 D 1911 D 1915 D 1919
D 1906 D 1910 D 1914 D 1918
・・・
D 2 D 6 D 10 D 14
D 1 D 5 D 9 D 13
・・・
D 1905 D 1909 D 1913 D 1917
[9：0] [9：0] [9：0] [9：0][9：0] [9：0] [9：0] [9：0]
[9：0] [9：0] [9：0] [9：0][9：0] [9：0] [9：0] [9：0]
[9：0] [9：0] [9：0] [9：0][9：0] [9：0] [9：0] [9：0]
[9：0] [9：0] [9：0] [9：0][9：0] [9：0] [9：0] [9：0]
1CH 2CH 3CH 4CH
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