AT&T PC 6300 - Page 222

DIAGNOSTICS
above. Additionally, the 8259 Interrupt Controller's
interrupt mask is enabled to allow a timer interrupt, so that
the 8086 CPU and the 8259 Interrupt Controller interrupt
service procedure is thus tested.
19. The parallel printer port and the display are sent
confirmation that the MM58174 Real-Time Clock/Calendar
chip is functional. If the 8253 clock fails to interrupt within
the acceptable time interval, an "RT Clock Fail" error
message specifying the reason for failure is sent to the
display, and the CPU is halted.
20. The interrupt vectors (including the nonmaskable interrupts
due to parity errors during the RAM module test) are
initialized for normal operation.
22. The parallel printer port and the display are sent
confirmation that the RAM module is functional. The
display reports the successful completion of each bank test,
as it is tested. If a failure is detected, a "xxx kb RAM
Fail:cc:yOOO:zzzz:wwww:rrrr" error message is sent to the
display indicating the faulty location, and the CPU is halted.
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21. The RAM test is performed bank-by-bank based on the
system configuration. An address and fixed pattern test is ^
done. A nonmaskable interrupt occurring during this test j l
indicates that the memory parity circuitry has detected a W
parity error.
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