AT&T PC 6300 - Page 221

DIAGNOSTICS
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'/ 14. Initialize dummy interrupt vectors in lowest RAM bank.
13. Initialize RAM stack at top of lowest RAM bank.
fl,
15. Determine the system configuration from the switch
settings.
16. The 8259 Programmable Interrupt Controller and 8086 CPU
interrupt test is performed. Software interrupts are
generated by executing an INT HO directly and performing
a divide-by-zero operation. Also, the single-step,
nonmaskable, and breakpoint interrupts are tested. The
8086 CPU's software interrupt service procedure is thus
tested. The 8259 Interrupt Controller is initialized. A test
pattern interrupt mask is written to and read back from the
8259. The 8259 is programmed with all interrupts masked
off. The 8086 CPU's interrupts are enabled.
17. The parallel printer port and the display are sent
confirmation that the 8259 Interrupt Controller and the
software interrupts are functional. If the interrupt test
i \ fails, an "Interrupts Fail" error message is sent to the
display identifying the software/hardware interrupt failure,
and the CPU is halted.
18. The MM58174 Real-Time Clock test is performed. It is
n assumed, at first, that the battery-powered Real-Time
Clock/Calendar chip is correctly programmed with a valid
user-selected time. The Real-Time clock is read, the valid
n state saved, the chip's time and data registers verified by
writing and reading, and then the valid time written back to
the chip. Next, the remaining two 8253 counters are
programmed and tested as in the 8253 DMA timer test
4-13