Titanium Interfaces User Guide
mipi_ln_rule_tx_clock (error)
Message Serial and parallel clocks cannot be the same clock
To fix You cannot use the same clock for both the serial (FASTCLK_C or FASTCLK_D) and parallel
(SLOWCLK) clocks.
Message Serial clock name is not a PLL output clock
To fix Use a PLL output clock as the serial (FASTCLK_C or FASTCLK_D) clock.
Message Parallel clock name is not a PLL output clock
To fix Use a PLL output as the parallel (SLOWCLK) clock.
Message Serial and parallel clocks are not from the same PLL instance
To fix You need to use the same PLL to generate both clocks.
Message Expected clocks phase shift in <data/clock> mode: Serial: <int> degree Parallel: <int>
degree
Expected clocks phase shift in <data/clock> mode: Serial: <int> degree
Expected clocks phase shift in <data/clock> mode: Parallel: <int> degree
To fix You need to use specific phase shifts for the clocks. Use the phase shift given in the message.
Message One of the clock frequencies is 0
To fix The output clock frequency is invalid. FASTCLK_D and FASTCLK_C should be the same
frequency as the PHY. SLOWCLK should be 1/8 the PHY frequency. For example, if the PHY is
running at 800 MHz, FASTCLK_D and FASTCLK_C should be 800 MHz and SLOWCLK should
be 100 MHz.
Message Serial clock frequency has to be 8 times faster than parallel clock
To fix FASTCLK_D and FASTCLK_C should be the same frequency as the PHY. SLOWCLK should
be 1/8 the PHY frequency. For example, if the PHY is running at 800 MHz, FASTCLK_D and
FASTCLK_C should be 800 MHz and SLOWCLK should be 100 MHz.
mipi_ln_rule_tx_clock_region (error)
Message
Serial and Parallel clocks generated by PLL have to be driven to the same clock
network. <Serial | Parallel> clock <name> was generated by PLL output
clock 4 that connects to regional clock network
To fix In Ti35 and Ti60FPGAs, the PLL's output clock 4 can only drive the regional clock network.
You should use the other clock outputs for the serial and parallel clocks.
lvds_rule_tx_distance (error)
Message These HSIO GPIO must be placed at least 1 pair away from MIPI LANE <name> in order to
avoid noise coupling from GPIO to MIPI LANE: <violated list>
To fix When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO pins
between any GPIO and HSIO used as MIPI TX lanes in the same bank. This separation reduces
noise.
mipi_ln_rule_tx_empty_pins (error)
Message Empty pin names found: <list>
To fix Specify the missing pin names in the list.
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