Efinix Titanium - Chapter 13: SPI Flash Interface; About the SPI Flash Memory

Titanium Interfaces User Guide
Chapter 13
SPI Flash Interface
Contents:
• About the SPI Flash Memory
• Using the SPI Flash Interface
Titanium Ti35 and Ti60 FPGAs in the F100 package have an integrated SPI flash memory.
About the SPI Flash Memory
Titanium FPGAs in the F100S3F2 package include a SPI flash memory. The SPI flash
memory has a density of 16 Mbits and a clock rate of up to 85 MHz. In active configuration
mode, the FPGA is configured using the configuration bitstream in the SPI flash memory.
Typically you can fit two compressed bitstream images into the F100S3F2 SPI flash.
Important: You cannot enable the Titanium FPGA security features when using compressed bitstreams.
To use active programming mode for the Titanium F100S3F2 with the SPI flash memory,
you must use the SPI Active using JTAG Bridge configuration mode to configure the SPI
flash memory.
Learn more: Refer to the AN 033: Configuring Titanium FPGAs for information on programming the SPI
flash memory.
Figure 52: SPI Flash Memory Block Diagram
SPI Flash
Memory
SCLK
MOSI
CS_N
MISO
WP_N
HOLD_N
Table 81: SPI Flash Memory Signals (Interface to FPGA Fabric)
Signal Direction Description
SCLK Input Clock output to SPI flash memory.
MOSI Input Data output to SPI flash memory.
CS_N Input Active-low SPI flash memory chip select.
WP_N Input Active-low write protect signal.
HOLD_N Input Active-low hold signal.
MISO Output Data input from SPI flash memory.
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