Efinix Titanium - MIPI Groups by Package

Titanium Interfaces User Guide
MIPI Lane Pads
Table 52: MIPI Lane Pads
Signal Direction Description
P Output Differential pad P.
N Output Differential pad N.
MIPI Groups by Package
You can use multiple HSIO as MIPI D-PHY lanes to build complete MIPI interfaces with
one clock lane and up to 8 data lanes.
• For MIPI TX interfaces, you can use any lane anywhere on the FPGA.
• For MIPI RX interfaces, the number of data lanes is restricted by the number of lanes in
the MIPI group. These groups vary depending on the package.
The following figures show the MIPI RX groups for each package. The Resource Assigner
also shows the group in the Block Summary's Feature field.
Figure 38: 64-Ball WLCSP MIPI RX Groups
I6
I0
C C
C
C
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
A
B
C D E F G H
A
B
C D E F G H
MIPI RX group I6
MIPI RX group I0
C Clock lane
Not in MIPI RX group
CRESET_N
VCCIO33_BL
TMS
TCK
TDI
GPIOR_P_00
PLLIN0
REF_RES_4A
GND
GPIOL_N_18
GPIOL_P_18
PLLIN0
GPIOL_N_17
GPIOL_N_15
TEST_N
GND
VCCA_TL
GPIOL_P_17
EXTFB
GPIOL_N_10
CLK3_N
GPIOL_N_04
CDI3
VCCIO1B_2A
GPIOL_N_03
CDI1
GPIOL_P_10
CLK3_P
GPIOL_N_08
CLK1_N
GPIOL_P_04
CDI2
GPIOL_P_03
CDI0
VCC
GPIOL_P_08
CLK1_P
VCC
GPIOL_N_02
CSO
CDONE
GPIOL_P_02
CSI
GND
GPIOL_N_01
CCK
GPIOL_P_01
SSL_N
REF_RES_1A
VCCIO1A_4B
TDO
GPIOL_P_15
NSTATUS
REF_RES_2A
REF_RES_3A
GPIOL_N_13
CBSEL1
GPIOL_P_13
CBSEL0
GPIOR_P_09
CLK10_P
REF_RES_1B
GPIOR_N_02
CDI25
GPIOR_N_03
CDI27
GND
GPIOR_P_02
CDI24
GPIOR_P_03
CDI26
VCCAUX GND
VCCIO2B_3A
_3B_4A
VCC
VCCA_BR
GPIOR_N_01
CDI23
GPIOR_N_00
CDI22
GPIOR_P_01
EXTFB
GND
GPIOR_N_09
CLK10_N
GPIOR_P_05
CDI30
GPIOR_N_05
CDI31
GPIOR_P_04
CDI28
GPIOR_N_04
CDI29
REF_RES_3B
VCC
GND
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