Titanium Interfaces User Guide
Revision History
Table 83: Revision History
Date Version Description
February 2022 2.0 Added Titanium DDR block interface description.
Added Titanium MIPI DPHY interface block description.
HVIO I/O banks support dynamic voltage shifting. (DOC-444)
Added MIPI RX clock groups for F484 package.
Added interface floorplan for F484 package.
New design rules: io_bank_rule_mode_sel, io_bank_rule_dyn_voltage.
Updated label for Ti60 W64 pin A7. (DOC-651)
November 2021 1.1 Updated PLL Block Diagram to indicate F
PLL
.
Updated JTAG mode connection diagram. (DOC-546)
Updated PLL phase-shift descriptions. (DOC-570)
PLL outputs lock on the negative clock edge. (DOC-552)
Added example PLL zero-delay buffer implementation. (DOC-551)
Added an example for the PLL outputs for the Create a MIPI TX Interface
topic. (DOC-580)
New design rule: clock_rule_lvds_rx_clock_source. This rule is effective
with Efinity patch v2021.1.4.10. (DOC-589)
New design rules: clock_rule_pll_ref_clock_lvds_rx, pll_rule_pll_freq,
lvds_rule_tx_clock_region, lvds_rule_rx_clock_region,
lvds_rule_rx_dpa_serial, and mipi_ln_rule_tx_clock_region.
June 2021 1.0 Initial release for Efinity software v2021.1.
www.efinixinc.com 138
To Previous Page
Loading...