Efinix Titanium - Chapter 9: MIPI RX;TX Lane Interface; HSIO Configured as MIPI Lane

Titanium Interfaces User Guide
Chapter 9
MIPI RX/TX Lane Interface
Contents:
• HSIO Configured as MIPI Lane
• MIPI Groups by Package
• Using the MIPI TX Lane or MIPI RX Lane Block
• Create a MIPI TX Interface
• Create a MIPI RX Interface
• Design Check: MIPI Lane Messages
Each HSIO block can use a pair of I/O pins as a MIPI RX or TX data lane or clock lane.
HSIO Configured as MIPI Lane
You can configure the HSIO block as a MIPI RX or TX lane. The block supports
bidirectional data lane, unidirectional data lane, and unidirectional clock lane which can run
at speeds up to 1.5 Gbps. The MIPI lane operates in high-speed (HS) and low-power (LP)
modes. In HS mode, the HSIO block transmits or receives data with x8 serializer/deserializer.
In LP mode, it transmits or receives data without deserializer/serializer.
The MIPI lane block does not include the MIPI D-PHY core logic. A full MIPI D-PHY
solution requires:
• Multiple MIPI RX or TX lanes (at least a clock lane and a data lane)
• Soft MIPI D-PHY IP core programmed into the FPGA fabric
The MIPI D-PHY standard is a point-to-point protocol with one endpoint (TX) responsible
for initiating and controlling communication. Often, the standard is unidirectional, but when
implementing the MIPI DSI protocol, you can use one TX data lane for LP bidirectional
communication.
The protocol is source synchronous with one clock lane and 1, 2, 4, or 8 data lanes. The
number of lanes available depends on which package you are using. A dedicated HSIO block
is assigned on the RX interface as a clock lane while the clock lane for TX interface can use
any of the HSIO block in the group.
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