Efinix Titanium - DDR Interface Designer Settings

Titanium Interfaces User Guide
DDR Interface Designer Settings
The following tables describe the settings for the Titanium DDR block in the Interface
Designer.
Table 21: Base Tab
Parameter Choices Notes
Instance Name User defined Indicate the DDR instance name. This name is the prefix for all
DDR signals.
DDR Resource None, DDR_0 Only one resource available.
Data Width 16, 32 Choose the DQ width. Default: 16
Physical Rank 1, 2 Default: 1
PHY Clock CLKIN 0,
CLKIN 1, CLKIN 2
Choose which PLL resource to use as the PHY clock.
CLKIN 0—PLL_TL0 (default)
CLKIN 1—PLL_TL1
CLKIN 2—PLL_TL2
Table 22: Config Tab
Option Choices Notes
<description>
Pin Name
User defined Configuration and control pins. You can use the default names or specify
your own.
Table 23: Controller Tab
Option Choices Notes
Clock to
Controller Pin
Name
User defined Enter the clock pin name.
Invert Clock to
Controller Pin
On or off Turn on if you want to invert the clock.
Default: off
<description>
Pin Name
User defined Controller pins. You can use the default names or specify your own.
Table 24: Control Register Tab
Option Choices Notes
Enable Register
Configuration
On or off Turn on to enable the control register for dynamic reconfiguration.
Invert AXI
Control Register
Clock Pin
On or off Turn on if you want to invert the clock.
Default: off
<description>
Pin Name
User defined Controller pins. You can use the default names or specify your own.
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