Efinix Titanium - Create a RX Deserializer Interface

Titanium Interfaces User Guide
Option Description
Mode output
Register Option register
Enable Serialization Turn on
Clock Pin Name Use the slow clock output name that corresponds to the PLL you
chose.
Serial Clock
Pin Name
Use the fast clock output name that corresponds to the PLL you
chose.
4. Repeat step 3 for each TX serializer you want to implement.
Create a RX Deserializer Interface
The following figure shows a completed RX deserializer interface, the deserialization width is
4 and m is the number of RX lanes.
Figure 21: Complete RX ISerializer nterface Block Diagram
FPGA
PLL
Core
INCLK
INFASTCLK
Deserializer
IN[3:0]
GPIO RX0
Deserializer
IN[3:0]
GPIO RXm
Interface Blocks
m is the number
GPIO
PLL_CLKIN
Follow these steps to build this interface using the Efinity
®
Interface Designer.
1. Add a PLL block with the following settings:
Option Description
Resource You can use any PLL resource.
Reference
Clock Mode
Any
Reference Clock
Frequency
Any
Output Clock Define the output clocks so that you have one for the fast clock
(serial) and one for the slow clock (parallel).
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