Efinix Titanium - Design Check: PLL Errors

Titanium Interfaces User Guide
The following code example shows an .isf that implements a zero-delay buffer for the Ti60
F225.
# Efinity Interface Configuration
# Version: 2021.1.165.2.19
# Date: 2021-09-23 15:23
#
# Copyright (C) 2017 - 2021 Efinix Inc. All rights reserved.
#
# Device: Ti60F225
# Package: 225-ball FBGA (preliminary)
# Project: r4000
# Configuration mode: active (x1)
# Timing Model: C4 (preliminary)
# Create instance
design.create_clockout_gpio("clkout")
design.create_pll_ext_fb_gpio("fbk_clk")
design.create_pll_input_clock_gpio("ref_clk")
design.create_block("pll_inst1","PLL")
# Set property, non-defaults
design.set_property("clkout","OUT_CLK_PIN","clk")
design.set_property("pll_inst1","CLKOUT0_EN","1","PLL")
design.set_property("pll_inst1","CLKOUT1_EN","0","PLL")
design.set_property("pll_inst1","CLKOUT2_EN","0","PLL")
design.set_property("pll_inst1","CLKOUT3_EN","0","PLL")
design.set_property("pll_inst1","CLKOUT4_EN","0","PLL")
design.set_property("pll_inst1","REFCLK_SOURCE","EXTERNAL","PLL")
design.set_property("pll_inst1","CLKOUT0_DIV","82","PLL")
design.set_property("pll_inst1","CLKOUT0_DYNPHASE_EN","0","PLL")
design.set_property("pll_inst1","CLKOUT0_PHASE_SETTING","0","PLL")
design.set_property("pll_inst1","CLKOUT0_PIN","clk","PLL")
design.set_property("pll_inst1","EXT_CLK","EXT_CLK0","PLL")
design.set_property("pll_inst1","LOCKED_PIN","","PLL")
design.set_property("pll_inst1","M","1","PLL")
3design.set_property("pll_inst1","N","1","PLL")
4design.set_property("pll_inst1","O","2","PLL")
design.set_property("pll_inst1","OUTPUT_CLOCKS_INVERTED","0","PLL")
design.set_property("pll_inst1","PHASE_SHIFT_ENA_PIN","","PLL")
design.set_property("pll_inst1","PHASE_SHIFT_PIN","","PLL")
design.set_property("pll_inst1","PHASE_SHIFT_SEL_PIN","","PLL")
design.set_property("pll_inst1","REFCLK_FREQ","33.33","PLL")
design.set_property("pll_inst1","RSTN_PIN","","PLL")
design.set_property("pll_inst1","FEEDBACK_MODE","EXTERNAL","PLL")
design.set_property("pll_inst1","FEEDBACK_CLK","CLK0","PLL")
# Set resource assignment
design.assign_pkg_pin("clkout","M7")
8design.assign_pkg_pin("ref_clk","P2")
9design.assign_pkg_pin("fbk_clk","R6")
10design.assign_resource("pll_inst1","PLL_BL0","PLL")
Design Check: PLL Errors
When you check your design, the Interface Designer applies design rules to your
configuration settings. The following tables show some of the error messages you may
encounter and explains how to fix them.
pll_rule_dynamic_shift_feedback (error)
Message Output clock <name> used as feedback cannot be set with dynamic phase shift
To fix If you are using a PLL output clock for feedback, you cannot use dynamic phase shifting.
Instead, specify a phase.
www.efinixinc.com 126