Titanium Interfaces User Guide
Chapter 10
MIPI D-PHY Interface
Contents:
• MIPI RX D-PHY
• MIPI TX D-PHY
• MIPI DPHY TX Interface Designer Settings
• MIPI DPHY RX Interface Designer Settings
Important: All information is preliminary and pending definition.
In addition to the HSIO, which you can configure as MIPI RX or TX lanes, Titanium
FPGAs have hardened MIPI D-PHY blocks, each with 4 data lanes and 1 clock lane. The
MIPI D-PHY RX and MIPI D-PHY TX can operate independently with dedicated I/O
banks.
You can use the hardened MIPI D-PHY blocks along with the HSIO configured as MIPI
D-PHY lanes to create systems that aggregate data from many cameras or sensors.
The MIPI TX/RX interface supports the MIPI D-PHY specification v1.2. It has the following
features:
• Programmable data lane configuration supporting up to 4 lanes
• High-speed mode supports up to 2.5 Gbps data rates per lane
• Operates in continuous and non-continuous clock modes
• Supports Ultra-Low Power State (ULPS)
MIPI RX D-PHY
The MIPI RX D-PHY is a receiver interface designed to receive data and the control
information of MIPI CSI, DSI, or other associated protocols. The MIPI RX D-PHY
comprises of one clock lane and up to four data lanes for a single-channel configuration. The
MIPI RX D-PHY also interfaces with MIPI-associated protocol controllers via a standard
MIPI D-PHY PHY Protocol Interface (PPI) that supports the 8- or 16-bit high-speed
receiving data bus.
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