Titanium Interfaces User Guide
Chapter 5
GPIO Interface
Contents:
• Types of GPIO
• Features for HVIO and HSIO Configured as GPIO
• About the HVIO Interface
• About the HSIO Interface
• HSIO Configured as GPIO
• Using the GPIO Block
• Using the GPIO Bus Block
• Create a TX Serializer Interface
• Create a RX Deserializer Interface
• Design Check: GPIO Messages
Titanium FPGAs have general-purpose I/O (GPIO) pins that allow the FPGA to
communicate with other components on your circuit board. When you create your RTL
design in the Efinity
®
software, you use the Interface Designer to add GPIO blocks for each
input, output, or bi-directional pin in your design.
Titanium GPIO pins have various features, depending on the position of the pin and which
package you are using. Refer to the Resource Assigner in the Interface Designer for the
features of the GPIO pin you want to use.
• GPIO that provide normal functionality
• GPIO with the double-data I/O (DDIO) feature that can capture twice the data
• HSIO as GPIO where the HSIO pin acts as a GPIO
The following sections describe the GPIO interface and how to use it in your design.
Types of GPIO
The Titanium FPGA supports two types of GPIO:
• High-voltage I/O (HVIO)—Simple I/O blocks that can support single-ended I/O standards.
• High-speed I/O (HSIO)—Complex I/O blocks that can support single-ended and
differential I/O functionality.
The I/O logic comprises three register types:
• Input—Capture interface signals from the I/O before being transferred to the core logic
• Output—Register signals from the core logic before being transferred to the I/O buffers
• Output enable—Enable and disable the I/O buffers when I/O used as output
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