Titanium Interfaces User Guide
Chapter 2
Device Settings
Contents:
• Configuration Interface
• Design Check: Configuration Messages
• I/O Banks Interface
• Titanium I/O Banks
• Dynamic Voltage Support
• Design Check: I/O Bank Messages
The Interface Designer has device-wide settings for I/O banks and configuration.
Configuration Interface
The Configuration device-wide setting lets you control or monitor configuration using the
FPGA design implemented in the FPGA core.
Enable Internal Configuration
Efinix
®
FPGAs have an internal reconfiguration feature that allows you to control
reconfiguration of the FPGA from within the FPGA design. Leave this feature disabled
unless you want to use internal reconfiguration.
To enable internal reconfiguration:
1. Click Device Setting > Configuration.
2. In the Block Editor Remote Update tab, turn on Enable Internal Reconfiguration
Interface.
3. Indicate the name of the clock pin that will control the internal reconfiguration.
4. Define the FPGA pins that the interface uses.
5. Save.
Note: Refer to AN 010: Using Internal Reconfiguration in Trion and Titanium FPGAs for instructions on
how to use this feature.
About SEU Detection
An SEU happens when an environmental factor, such as background radiation, causes a
digital circuit to malfunction. For FPGAs, the most frequent (and most worrisome) outcome
of an SEU is that a CRAM bit is changed from its programmed value. Designs may not use
every CRAM bit in the FPGA, so an SEU may or may not cause the FPGA to malfunction.
However, in many situations the safest course of action is to assume that the FPGA's
behavior is corrupted until it is reconfigured.
Titanium FPGAs contain built-in circuitry to help detect SEUs. This circuitry periodically
monitors the FPGA's CRAM, detects if a CRAM value has changed from the programmed
state, and sends status signals to user logic. The user logic can optionally trigger the FPGA to
reconfigure using the SEU detection circuitry.
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