Titanium Interfaces User Guide
Signal Direction Description
SHIFT[2:0] Input (Optional) Dynamically change the phase shift of the output selected to
the value set with this signal.
Possible values from 000 (no phase shift) to 111 (3.5 F
PLL
cycle delay). Each
increment adds 0.5 cycle delay.
SHIFT_SEL[4:0] Input (Optional) Choose the output(s) affected by the dynamic phase shift.
SHIFT_ENA Input (Optional) When high, changes the phase shift of the selected PLL(s) to the
new value.
Using the PLL V3 Block
Titanium FPGAs have a PLL block that lets you configure the reference clock, feedback
options, frequency, and output clocks for the PLL. This PLL is referenced as V3. You set
up the PLL using the PLL Clock Calculator, which provides an easy-to-use graphical way to
specify the frequencies and other settings.
• In the PLL's Properties tab, you specify general settings such as the instance name, PLL
resource, clock source, and external clock.
• Click the Automated Clock Calculation button to open the PLL Clock Calculator.
Reference Clock Settings
The PLL has four possible reference clocks. Depending on the PLL, one or two of the clocks
can come from the FPGA core, and two or three can come from off chip. You select the
clocks using the Clock Source drop-down box:
• core—The PLL reference clock comes from the FPGA core.
• external—Enables clock 0, 1, or 2. The PLL reference clock comes from an external pin.
The GUI displays the resource(s) that can be the reference clock.
Note: In this mode, a GPIO block with a pll_clkin connection type must generate
the reference clock(s). The software displays which resource(s) you can use (and the
instance name if you have created it).
1. Add a GPIO block.
2. Enter the instance name.
3. Choose input as the mode.
4. Choose pll_clkin as the connection type.
5. In the Resource Assigner, assign it to the resource shown in the PLL's Properties tab.
• dynamic—Enables all four clocks; requires a clock selector bus to choose the clock
dynamically. The GUI displays the resource(s) that can be the reference clock.
Using the PLL Clock Calculator
The PLL Clock Calculator provides a graphical way for you to set up the advanced PLL
block. When you open the calculator, the GUI appears in automatic mode, which provides
basic settings. You can:
• Choose the feedback mode (Local, Core, or External).
• Turn signals on (gray x) or off (green arrow) by clicking the icons next to the signal.
• Specify the signal names.
• Specify the phase shift.
• Choose which clock has feedback (for core feedback mode).
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