Titanium Interfaces User Guide
Interface Blocks
Titanium FPGAs support a variety of interface blocks. The available blocks differ depending
on which FPGA you target. You need to assign a resource for every block you use.
The following table describes the interface blocks supported in the Efinity
®
software version
2021.2.
Table 1: Titanium Interface Blocks
Interface Ti35 Ti60 Ti90 Ti120 Ti180
DDR
GPIO
GPIO bus
I/O bank
JTAG User TAP
LVDS TX
LVDS RX
Bidirectional
LVDS
MIPI DPHY
MIPI TX Lane
MIPI RX Lane
PLL (V3)
Oscillator
All interface blocks have an instance name that must be a unique identifier. When you add
a new block, the Interface Designer gives the block a unique default name, which you can
change.
Note: Many fields in the Block Editor allow arbitrary names. After you type a new name, press Enter or
click Save to save the name.
Pin names are the top-level ports of the design implemented in the core that connect to the
interface block. These names must be legal Verilog HDL or VHDL identifiers.
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