Efinix Titanium - Interface Designer Output Files; Scripting an Interface Design

Titanium Interfaces User Guide
When working with the .csv file:
• Add your assignments to the Instance Name and Mode columns.
• Do not modify the package pin-pad names.
• For the mode, specify: input, output, inout, clkout, or none
Note: You cannot make advanced settings such as alternate connections or
registering. To make these settings, use the Block Editor.
When the software reads an imported .csv file, it performs a comparison between the .csv
assignments and the original GPIO block assignments and reports any issues. If the software
finds warnings, it displays them but allows you to finish the import. If it finds errors, it will
not finish the import. When importing, the software:
• Deletes instances that you removed
• Creates newly defined instances
• Replaces instances you renamed with the new name
Interface Designer Output Files
When you generate constraint files, the Interface Designer creates the following output files.
You can view them in the Interface section of the Result pane.
• <project name>.interface.csv—Constrains the FPGA design pins used in the interface
between the core and the periphery.
• <project name>.pt.rpt—Provides information about the interface.
• <project name>.pinout.csv—Contains the board design pinout in CSV format.
• <project name>.pinout.rpt—Has the board design pinout in a nicely formatted text file
format.
• <project name>.pt_timing.rpt—Timing report for the Titanium interface logic.
• <project name>.pt.sdc—Template SDC file to constrain the FPGA design pins based
on the interface configuration.
• <project name>_template.v—Template Verilog HDL file defining the FPGA design
pins based on the interface configuration.
Scripting an Interface Design
Python is an interpreted, object-oriented, high-level programming language with dynamic
semantics.
(2)
Efinix distributes a copy of Python 3 with the Efinity
®
software to support point
tools such as the Debugger and to allow users to write scripts to control compilation.
You use the Efinity
®
Interface Designer to build the peripheral portion of your design,
including GPIO, LVDS, PLLs, MIPI RX and TX lanes, and other hardened blocks. Efinix
provides a Python 3 API for the Interface Designer to let you write scripts to control the
interface design process. For example, you may want to create a large number of GPIO, or
target your design to another board, or export the interface to perform analysis. This user
guide describes how to use the API and provides a function reference.
Learn more: Refer to the Python web site, www.python.org/doc, for detailed documentation on the
language.
(2)
Source: What Is Python? Executive Summary
www.efinixinc.com 15