Efinix Titanium - Design Check: Clock Control Messages

Titanium Interfaces User Guide
Design Check: Clock Control Messages
When you check your design, the Interface Designer applies design rules to your clock and
control settings. The following tables show some of the error and warning messages you may
encounter and explains how to fix them.
clock_rule_capacity (error)
Message Cannot connect to more than <int> different clocks per region (40 rows) on left and right and
<int> clocks on the top or bottom
To fix You cannot have more than 32 clocks (GPIO configured in clkout mode) coming from the
core. You need to remove some clocks.
Message Cannot connect to more than <int> different clocks per region (40 rows) on left and right
To fix You are using more clocks that are available for the local region. Remove some clocks. See
"Driving the Local Network" in the data sheet.
Message Cannot connect to more than <int> different clocks on top and bottom
To fix You are using more clocks than are available on the top and bottom local regions. Remove
some clocks. See "Driving the Local Network" in the data sheet.
clock_rule_max_count (error)
Message Number of core clock used exceeds max limit of <int>
To fix You cannot have more than 32 clocks (GPIO configured in clkout mode) coming from the
core. You need to remove some clocks.
clock_rule_lvds_rx_clock_source (error)
Message The following PLL instance has output clocks driving LVDS Rx instance on different sides pair -
[<PLL instance>: [<clock name>(<LVDS instance>)]]
To fix The PLL output clocks go to multiple LVDS RX on different sides of the FPGA. The fast clock
and slow clock can only drive I/O from the same left/right or top/bottom sides. For example,
TR_PLL generates rx_fastclk and rx_slowclk for LVDS in the right-side bank. These clocks can
also drive the LVDS channel on the left bank. However, they cannot drive LVDS in the top or
bottom banks.
clock_rule_pll_ref_clock_lvds_rx (error)
Message The following PLL instance has reference clock that does not match the side of the LVDS Rx
instance driven by its output clocks - [<PLL instance>: [<clock name>(<LVDS instance>)]]
To fix Choose the PLL reference clock that is on the same side as the LVDS that the output clock is
driving. For example, if TR_PLL is driving LVDS on the right side, the PLL external source clock
should also come from the I/O on the right side.
clock_rule_undefined_name (warning)
Message No clock source defined
To fix All clocks in the periphery must be defined in the Interface Designer (GPIO clock, oscillator,
PLL, LVDS GCLK, MIPI D-PHY CLK). This warning indicates that you have not defined it as an
interface block. If the clock is generated in the core you can ignore this warning.
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