Titanium Interfaces User Guide
Chapter 6
LVDS Interface
Contents:
• HSIO Configured as LVDS
• Using the LVDS Block
• Create an LVDS TX Interface
• Create an LVDS RX Interface
• Design Check: LVDS Errors and Warnings
Each HSIO block can use a pair of I/O pins as an LVDS receiver (RX), transmitter (TX), or
bidirectional (RX/TX) signal.
HSIO Configured as LVDS
You can configure each HSIO block in RX, TX, or bidirectional LVDS mode. As LVDS, the
HSIO has these features:
• Programmable V
OD
, depending on the I/O standard used.
• Programmable pre-emphasis.
• Up to 1.5 Gbps.
• Programmable 100 Ω termination to save power (you can enable or disable it at runtime).
• LVDS input enable to dynamically enable/disable the LVDS input.
• Support for full rate or half rate serialization.
• Up to 10-bit serialization to support protocols such as 8b10b encoding.
• Programmable delay chains.
• Optional 8-word FIFO for crossing from the parallel (slow) clock to the user’s core clock
to help close timing (RX only).
• Dynamic phase alignment (DPA) that automatically eliminates skew for clock to data
channels and data to data channels by adjusting a delay chain setting so that data is
sampled at the center of the bit period.
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