Efinix Titanium - Chapter 14: Interface Floorplans

Titanium Interfaces User Guide
Chapter 14
Interface Floorplans
Note: The numbers in the floorplan figures indicate the HVIO and HSIO number ranges. Some packages
may not have all HVIO or HSIO pins in the range bonded out.
Floorplan Diagram for FPGAs in W64 Packages
Figure 53: Ti60 FPGAs
Right
Left
1A
Quantum
Compute Fabric
Dimensions not to scale
9
1B
18
0
8
2A
9 17
2BTL TR
BR
PLL_TL
PLL_BR0 8
4B
9 17
4A
8
BL
I/O bank
Dedicated blocks
PLL
HSIO
0
3B
10
3A
19
9
0
Floorplan Diagram for FPGAs in F100 Packages
Figure 54: Ti35 and Ti60 FPGAs
Right
Left
1A
Quantum
Compute Fabric
Dimensions not to scale
9
1B
18
0
8
2A
9 17
2BTL TR
BR
PLL_TL PLL_TR
PLL_BR0 8
4B
9 17
4A
8
BL
I/O bank
Dedicated blocks
PLL
HSIO
0
3B
10
3A
19
9
0
www.efinixinc.com 135