Efinix Titanium - Page 136

Titanium Interfaces User Guide
Floorplan Diagram for FPGAs in F225 Packages
Figure 55: Ti35 and Ti60 FPGAs
Right
Left
1A
Quantum
Compute Fabric
Dimensions not to scale
9
1B
18
0 8
2A
9 17
2B
TL
TR
BR
PLL_TL PLL_TR
PLL_BR
0
8
4B
9 17
4A
8
BL
0
I/O bank
HVIO
Dedicated blocks
PLL
HSIO
0
2
3
11
3B
10
3A
19
9
29
0
21
20
12
PLL_BL
Floorplan Diagram for FPGAs in F484 Packages
Figure 56: Ti90, Ti120, and Ti180 FPGAs
Right
Left
Quantum
Compute Fabric
Dimensions not to scale
DDR
00
10
2A
11 22
2B
TL
TR
BR
PLL_TR
PLL_BR
00
10
4C
11 22
4B
BL
I/O bank
HVIO
Dedicated blocks
PLL
HSIO
26
55
3B
32
3A
45
31
73
16
65
64
56
PLL_BL0
MIPI block
DDR block
TX
MIPI 0
RX
TX
MIPI 1
RX
00
25
TX
MIPI 2
RX
TX
MIPI 3
RX
23 34
2C
3C
15
00
23 34
4A
PLL_BL1
PLL_BL2
PLL_TL0
PLL_TL1
PLL_TL2
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