Titanium Interfaces User Guide
Clock Sources that Drive the Global and
Regional Networks
The Titanium global and regional networks are highly flexible and configurable. Clock
sources can come from interface blocks, such as GPIO or PLLs, or from the core fabric.
Note: For more information on the clock sources that can drive the global and regional networks, refer to
the data sheet.
Table 6: Clock Sources that Drive the Global and Regional Networks
Source Description
GPIO Supports GCLK, GCTRL, RCLK, RCTRL. (Only the P resources support this
connection type).
LVDS RX Supports GCLK and RCLK.
MIPI RX Lane (configured
as clock lane)
Supports GCLK (default) and RCLK. You can only use resources that are identified as
clocks.
PLL Ti35, Ti60: Output clocks 0 - 3 connect to the global network.
Output clock 4 only connects to the regional network in the top or bottom interface
regions (depending on the location of the PLL) and can only drive interface blocks
on the top or bottom of the FPGA.
Refer to Driving the Regional Network.
Oscillator
Connects to global buffer.
(4)
Core Signals from the core logic can drive the global or regional network.
Note: Some clock sources can drive both the global and regional networks. See Driving both the Global
and Regional Networks on page 27 for instructions on using both.
(4)
The Ti60ES oscillator can only drive the core.
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