Titanium Interfaces User Guide
Design Check: I/O Bank Messages
When you check your design, the Interface Designer applies design rules to your
configuration settings. The following tables show some of the error and warning messages
you may encounter and explains how to fix them.
io_bank_rule_dyn_voltage (error)
Message
Bank <name> does not support dynamic voltage
To fix
Choose an HVIO I/O bank that supports dynamic voltage.
io_bank_rule_lvds (error)
Message I/O Voltage has to be set to <#> when LVDS is used
To fix Set the I/O bank voltage to 1.8 V if you are using pins in that bank for LVDS. Note: you cannot
use MIPI lanes and LVDS pins in the same I/O bank because they require different voltages.
io_bank_rule_mipi_dphy (error)
Message I/O Voltage has to be set to <#> when MIPI LANE is used
To fix When the HSIO pins are used as MIPI lanes, the I/O bank voltage must be 1.2 V. Note: you
cannot use MIPI lanes and LVDS pins in the same I/O bank because they require different
voltages.
io_bank_rule_es_device (error)
Message Unsupported 2.5 V in ES device
To fix The Ti60ES FPGA does not support 2.5 V. Choose another voltage.
io_bank_rule_voltage_assignment (error)
Message I/O Voltage <voltage> is not supported for the bank
To fix Different I/O banks support different voltages. Choose a voltage that the I/O bank supports
(refer to Titanium I/O Banks on page 21).
io_bank_rule_mode_sel (error)
Message
Empty Mode Select pin name found
To fix Enter the name of the mode select pin.
io_bank_rule_vref (warning)
Message It is not advisable to enable single-ended input SSTL/HSTL with LVDS Tx common mode in
the following banks <banks>
To fix An LVDS block with the Output Differential Type set to custom requires a VREF pin. A GPIO
block using the single-ended SSTL or HSTL I/O standard also uses a VREF. The reference
voltages for these standards is unlikely to be the same, so you should not use them in the
same I/O bank. Instead, move one of the blocks to another bank.
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