Efinix Titanium - Chapter 4: DDR Interface; About the DDR DRAM Interface

Titanium Interfaces User Guide
Chapter 4
DDR Interface
Contents:
• About the DDR DRAM Interface
• DDR Interface Designer Settings
Some Titanium FPGAs have a hardened IP interface block to communicate with off-the-shelf
memories. Refer to the Package/Interface Support Matrix on page 8 to find out if your
FPGA supports DDR.
About the DDR DRAM Interface
Important: All information is preliminary and pending definition.
The DDR PHY interface supports LPDDR4 and LPDDR4x memories with 1 DQ widths
and a memory controller hard IP block. The memory controller provides two full-duplex
AXI4 buses to communicate with the FPGA core.
Note: The DDR PHY and controller are hard blocks; you cannot bypass the DDR DRAM memory controller
to access the PHY directly for non-DDR memory controller applications.
Table 8: DDR DRAM Performance
DDR DRAM Interface Maximum Data Rate (Mbps) per Lane
LPDDR4/LPDDR4x
(5)
The DDR DRAM block uses an optional AXI4 bus to read/write the DDR configuration
registers. You can use this bus to fine tune the DDR PHY for high performance.
(5)
Pending definition.
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