Efinix Titanium - Page 118

Titanium Interfaces User Guide
Table 71: Data Lane Tab
Option Choices Notes
Enable Turn-around Feature in
Data Lane 0
On or off Lane 0 can operate as a bi-directional data lane when this
option is on.
Default: on
Number of data lanes 1, 2, 4 Choose the number of lanes. Default: 4
Width of the data bus 8, 16 Specify the width. Default: 8
<description> Pin Name User defined Data lane pin names. Efinix recommends that you use the
defaults.
Table 72: Lane Mapping Tab
Parameter Choices Notes
Phy Lane n clk, data0.
data1, data2,
data3, unused
The MIPI TX block supports 4 data lanes and 1 clock lane.
Choose which lane to associate with the MIPI pad. The lane
mapping must be unique, which the software enforces.
Swap P&N Pin On or off Turn on to change which pin is P or N. This setting can be
helpful when laying out your board.
Table 73: Timing Tab
Parameter Notes
T
CYCLE_SEL
(ns)
T
PLL_FBK_FRA
(ns)
T
PLL_FBK_INT
(ns)
T
PLL_PRE_DIV
(ns)
T
CLANE_HS_CLK_POST_TIME
(ns)
T
CLANE_HS_CLK_PRE_TIME
(ns)
T
CLANE_HS_PRE_TIME
(ns)
T
CLANE_HS_TRAIL_TIME
(ns)
T
CLANE_HS_ZERO_TIME
(ns)
T
DLANE_HS_PRE_TIME
(ns)
T
DLANE_HS_TRAIL_TIME
(ns)
T
DLANE_HS_ZERO_TIME
(ns)
These are temporary parameters. The Interface
Designer will generate them in an upcoming release.
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