Efinix Titanium - Page 49

Titanium Interfaces User Guide
Figure 17: I/O Buffer Path for LVCMOS
HSIO Buffer
VREF
VREF
P
OE P
Buffer In P
Buffer Out P
N
OE N
Buffer In N
Buffer Out N
When using an HSIO with the HSTL or SSTL I/O standards, you must configure an I/O pad
of the standard's input path as a VREF pin. There is one programmable VREF per I/O bank.
Important: When configuring an I/O pad of the standard's input path as a VREF pin, you must use the
VREF from the same physical I/O bank even when the I/O banks are merged to share a common VCCIO
pin.
Figure 18: I/O Buffer Path for HSTL and SSTL
HSIO Buffer
VREF
VREF
P
OE P
Buffer In P
Buffer Out P
N
OE N
Buffer In N
Buffer Out N
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