Efinix Titanium - Page 51

Titanium Interfaces User Guide
Input Mode
Use input mode for input signals.
Table 35: Input Mode Options
Option Choices Description
Connection Type normal, gclk, gctrl,
pll_clkin, pll_extfb,
mipi_clkin, rclk, rctrl,
vref
Some pins have alternate functions, and you use this option to
choose the function. (This option only applies to pins that have
alternate functions. Refer to the data sheet for your FPGA for pin
information.) For example, a PLL can use a GPIO with an alternate
connection type as a reference clock.
Note: If you set the connection type to pll_clkin,
pll_extfb, or mipi_clkin, the signal is also available as a
regular input to the core.
Register Option register, none Choose whether the input is registered.
If you choose register:
• Define an input clock pin name.
• Turn clock inversion on or off.
• Under Double Data I/O Option, select one of the following:
none Do not use double data I/O.
normal Data is passed to the core on both the
positive and negative clock edges
resync Data is resynchronized to pass both data
signals on the positive clock edge. <pin
name>_hi is the positive edge and <pin
name>_lo is the negative edge.
pipeline Similar to resync except the data for both
signals starts on the same clock edge.
• To use the deserializer, turn on Enable Deserialization and specify
the serial clock pin name. (You cannot use the deserializer with
DDIO.)
Pull Option none, weak
pullup, weak
pulldown, dynamic
Specify if you want a pull option.
If you choose dynamic, you must also specify the Dynamic Pull Up
Enable Pin Name.
Enable Schmitt
Trigger
On or off Optionally enable a Schmitt trigger.
Enable Bus Hold On or off Optionally enable a bus hold.
Integer 0-15 For single-ended only. Choose the amount of static delay, each
step adds approximately 60 ps of delay.
You can only set the static delay for individual signals, not buses.
Static Delay Settting
0 - 63 For differential only: 64 steps with approximately 25 ps of delay
per step.
You cannot use the static delay and dynamic delay simultaneously.
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