Intel Embedded Intel486 User Manual

6-7
CACHE SUBSYSTEM
Figure 6-2. Direct Mapped Cache Organization
If the processor requests data at FFFFF8, the first step is to send the least significant 14 bits of
FFF8 to the cache tag RAM. If the tag field stored at FFF8 is FF (as shown in the diagram), then
a hit has occurred and the data word ‘‘B’’ is sent to the CPU. If the requested word has 020004,
then the tags would not match. In this case the tag RAM would be updated with the value 02 cor-
responding to the index 0004, and the data ‘‘D’’ would be replaced by the word at location
020004.
If the processor accesses locations that have the same index bits, then the cache would have to be
updated constantly. This type of program behavior is infrequent, however, so a direct mapped
32-Bit Processor Address
Cache/DRAM
Select
TAG Index
31
24
23 16 15 0
16 Mbyte DRAM 24 Bits
Main Memory - 16 MB
64 Kbyte Cache 16 Bits
TAG
Cache-64 Kbyte
Index
01
FF
00
01
00
0008
0004
0000
A
B
C
D
E
Y
B
Index
FFFC
FFF8
0008
0004
0000
A
D
C
E
FFFC
FFF8
0008
0004
0000
FFFC
FFF8
0008
0004
0000
32 Bits
DataTAG
FFFC
FFF8
Data

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English