EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
7-42
Table 7-12. 82596 Signals (Sheet 1 of 2)
Signal Type Description
Address and Data Buses
A31–A2 O Address
D31–D0 I/O Data
BE3#–BE0# O Byte-enables
BS16# I 16-bit data bus size
LE/BE# I Little endian or big endian byte ordering
DP3–DP0 I/O Data parity
PCHK# O Parity error
Cycle Definition and Control
ADS# O Address status
W/R# O Write or read
PORT#
†
I Port access
RDY# I Non-burst data ready
BRDY# I Burst data ready
BLAST# O Last burst cycle
Bus Control
CLK I Clock
RESET
†
I Reset
INT/INT# O Interrupt
BREQ I Bus request
HOLD O Bus hold request
HLDA I Bus hold acknowledgment
AHOLD
†
I Address hold request
BOFF# I Bus backoff
LOCK# O Bus lock
CA#
†
I Channel attention
†
Signals marked with a dagger are not included on, or operate differently than, the Intel486™ processor
bus.
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