8-21
SYSTEM BUS DESIGN
The chipset consists of two components: the system controller and the ISA bridge. The system
controller integrates the second-level (L2) cache controller and the DRAM controller. The cache
controller supports both write-through and write-back cache policies and cache sizes from 64
Kbytes to 512 Kbytes in an interleaved or non-interleaved configuration. The DRAM controller
interfaces main memory to the Host bus and the PCI bus. The system controller supports a two-
way interleaved DRAM organization for optimum performance. Up to ten single-sided SIMMs
or four double-sided and two single-sided SIMMs provide a maximum of 128 Mbytes of main
memory. The system controller provides memory write posting to PCI for enhanced CPU-to-PCI
memory write performance. In addition, the system controller provides a high performance PCI
local bus IDE interface. Figure 8-6 shows a block diagram of the system controller component of
the PCI chip set.
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